PT Symmetric, Hermitian and P-Self-Adjoint Operators Related to Potentials in PT Quantum Mechanics

In the recent years a generalization $H=p^2 +x^2(ix)^\epsilon$ of the harmonic oscillator using a complex deformation was investigated, where \epsilon\ is a real parameter. Here, we will consider the most simple case: \epsilon even and x real. We will give a complete characterization of three different classes of operators associated with the differential expression H: The class of all self-adjoint (Hermitian) operators, the class of all PT symmetric operators and the class of all P-self-adjoint operators. Surprisingly, some of the PT symmetric operators associated to this expression have no resolvent set

LUX -- A Laser-Plasma Driven Undulator Beamline

The LUX beamline is a novel type of laser-plasma accelerator. Building on the joint expertise of the University of Hamburg and DESY the beamline was carefully designed to combine state-of-the-art expertise in laser-plasma acceleration with the latest advances in accelerator technology and beam diagnostics. LUX introduces a paradigm change moving from single-shot demonstration experiments towards available, stable and controllable accelerator operation. Here, we discuss the general design concepts of LUX and present first critical milestones that have recently been achieved, including the generation of electron beams at the repetition rate of up to 5 Hz with energies above 600 MeV and the generation of spontaneous undulator radiation at a wavelength well below 9 nm.Comment: submitte

Enhanced Radiation Hardness and Faster Front Ends for the Beetle Readout Chip

This paper summarizes the recent progress in the development of the 128 channel pipelined readout chip Beetle, which is intended for the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH detectors of LHCb. Deficiencies found in the front end of the Beetle Version 1.0 and 1.1 chips resulted in the submissions of BeetleFE 1.1 and BeetleFE 1.2, while BeetleSR 1.0 implements test circuits to provide future Beetle chips with logic circuits hardened against single event upset (SEU). Section I. motivates the development of new front ends for the Beetle chip, and section II. summarizes their concepts and construction. Section III. reports preliminary results from the BeetleFE 1.1 and BeetleFE 1.2 chips, while section IV. describes the BeetleSR 1.0 chip. An outlook on future test and development of the Beetle chip is given in section V